1. A Flexible Generator of Component Models. - 1. 1. Introduction. - 1. 2. G&D Generator. - 1. 3. A Flexible Generator. - 1. 4. Implementation of the Generator. - 1. 5. Experimental Results. - 1. 6. Conclusions and Future Work. - 2. What Makes an Asic Library Sign-Off. - 2. 1. Introduction. - 2. 2. Testing. - 2. 3. Accuracy. - 2. 4. Library Creation. - 2. 5. Conclusion. - 3. A Case History in Building Vital-Compliant Models. - 3. 1. Introduction: from VHDL to VITAL. - 3. 2. Evolution of VITAL Specification. - 3. 3. Simulation Performances. - 3. 4. Conclusion and Future Work. - 4. Modeling Multiple Driver Net Delay in Simulation. - 4. 1. Wire Delay. - 4. 2. Wire Delay Modeling Alternatives. - 4. 3. Modeling Wire Delay. - 4. 4. Wire Delay Model Integration. - 4. 5. Summary. - 5. Delphi: The Development of Libraries of Physical Models of Electronic Components for an Integrated Design Environment. - 5. 1. Background. - 5. 2. The DELPHI Project. - 5. 3. Preliminary Investigations of compact models for Mono-Chip Packages. - 5. 4. A Compact Model of a 208-Lead PQFP Package. - 5. 5. Concluding Remarks. - 6. VHDL Floating Point Operations. - 6. 1. Introduction. - 6. 2. Framework for VHDL Code. - 6. 3. Operations. - 6. 4. Validation and Benchmarking. - 6. 5. Package Usability. - 6. 6. Conclusions. - 7. Symbolic Model Checking with Past and Future Temporal Modalities: Fundamentals and Algorithms. - 7. 1. Introduction. - 7. 2. Fundamentals. - 7. 3. The Temporal Logic. - 7. 4. Algorithms of the Symbolic Model Checker. - 7. 5. Application to VHDL. - 7. 6. Conclusion. - 8. Krypton: Portable Non-Reversible Encryption for VHDL. - 8. 1. Introduction. - 8. 2. VHDL Source-Source Encryption. - 8. 3. LVS: A Compilation Environment for VHDL-Based Applications. - 8. 4. Running KRYPTON. - 8. 5. Example. - 8. 6. Conclusions and Perspectives. Language: English